17512LJC

• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA; requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions
• Supports XC4000EX/XL fast configuration mode (15.0
MHz)
• Low-power CMOS Floating Gate process
• Available in 5 V and 3.3 V versions
• Available in compact plastic packages: 8-pin PDIP,
20-pin SOIC, and 20-pin PLCC.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance a